题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	reg [7:0] sequence;		  
	reg pre_result, res;
	reg [31:0] cnt;

	initial begin
		match <= 0;
		sequence[7:0] <= 8'b0;
		pre_result <= 0;
		res <= 0;
		cnt[31:0] <= 32'b0000;
	end

	always @(rst_n) begin
		if (rst_n == 0) begin
			match <= 0;
			sequence[7:0] <= 8'b0;
			pre_result <= 0;
			res <= 0;
			cnt[3:0] <= 4'b0000;
		end
	end

	always @(posedge clk) begin 
		if (rst_n == 1) begin
			cnt <= cnt + 1'b1;
			sequence[7:1] <= sequence[6:0];
			sequence[0]   <= a;
		end
	end

	always @(cnt)
		if ((cnt >= 8) && (sequence[7:0] == 8'b01110001))
		    res <= 1;
		else  res <= 0 ;
	
	//always @(posedge clk) begin
	//	pre_result <= res;
	//end
	//always @(posedge clk) begin
	//	match <= pre_result;
	//end  
	always @(posedge clk) begin
		match <= res;
	end  
endmodule

--- :( 为啥没有Verilog代码样式 ---

请编写一个序列检测模块，检测输入信号a是否满足01110001序列，当信号满足该序列，给出指示信号match。

https://dev-private-public.oss-cn-hangzhou.aliyuncs.com/images/20220217/110_1645101347879/8F57F0D5835AE082EE03DAADC8ADBE73

模块的接口信号图如下：

https://uploadfiles.nowcoder.com/images/20220315/110_1647325145728/0E585C0568007132C050FAC65B6A5BB1

题目的时序图有问题，匹配后下一个clk就要match拉高，结果图片里是下下个clk。弄得我还考虑复杂了 :) :)😅