题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d, 
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [15:0] temp_data = 16'h0000;
reg[4:0] temp_out = 5'b00000;
reg temp_validout = 1'b0;

always@(posedge clk)
begin
    case(sel)
    0: begin temp_out <= 5'b00000; temp_validout <= 1'b0; temp_data <= d;end
    1: begin temp_out <= temp_data[3:0] + temp_data[7:4];   temp_validout <= 1'b1; end
    2: begin temp_out <= temp_data[3:0] + temp_data[11:8];  temp_validout <= 1'b1; end
    3: begin temp_out <= temp_data[3:0] + temp_data[15:12]; temp_validout <= 1'b1; end
    default: begin temp_out <= 5'bxxxxx; temp_validout <= 1'bx; end
    endcase
end

assign out = temp_out;
assign validout = temp_validout;

//*************code***********//
endmodule