题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);

	reg			rst_async_n;
	reg			set_d1;
	// *********************** 为满足题目的时序 ***************** //
	// 将复位设置成异步复位，同步释放
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n)
			rst_async_n <= 1'b0;
		else
			rst_async_n <= 1'b1;
	end
    // 将set信号打一拍
	always @(posedge clk or negedge rst_async_n) begin
		if(!rst_async_n)
			set_d1 <= 1'b0;
		else
			set_d1 <= set;
	end
	// ********************************************************** //
	// number
	always @(posedge clk or negedge rst_async_n) begin
		if(!rst_async_n)
			number <= 4'd0;
		else if(set_d1)
			number <= set_num;
		else
			number <= number + 1'b1;
	end
	
	// zero
	always@(*)begin
		if(!rst_async_n)
			zero = 0;
		else
			zero = (number == 4'b0);
	end
			




endmodule