题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
	reg					data_d;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_d <= 1'b0 ;
		end
		else begin
			data_d <= data_in ;
		end
	end
	assign data_tmp = data_in & (!data_d) ;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <=1'b0 ;
		end
		else begin
			data_out <= data_tmp ;
		end
	end
endmodule