题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
reg			[3:0]		data_reg;
always @(posedge clk_a or negedge arstn) begin
	if(!arstn) begin
		data_reg <= 4'b0 ;
	end
	else begin
		data_reg <= data_in ;
	end
end
reg					data_en_reg;
reg					data_en_reg_d1;
reg					data_en_reg_d2;

always @(posedge clk_a or negedge arstn) begin
	if(!arstn) begin
		data_en_reg <= 1'b0 ;
	end
	else begin
		data_en_reg <= data_en ;
	end
end
always @(posedge clk_b or negedge brstn) begin
	if(!arstn) begin
		data_en_reg_d1 <= 1'b0 ;
		data_en_reg_d2 <= 1'b0 ;

	end
	else begin
		data_en_reg_d1 <= data_en_reg ;
		data_en_reg_d2 <= data_en_reg_d1;
	end
end
always @(posedge clk_b or negedge brstn) begin
	if(!brstn) begin
		dataout <= 4'b0 ;
	end
	else if(data_en_reg_d2) begin
		dataout <= data_reg ;
	end
end
endmodule