题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
    
	wire [4:0] C;
	wire [3:0] G;
	wire [3:0] P;
	assign C[0] = C_1;
	genvar i;
	generate 
		for (i=0;i<=3;i=i+1) begin:lca
			assign G[i] = A_in[i] & B_in[i];
			assign P[i] = A_in[i] ^ B_in[i];
			assign C[i+1]  = G[i] | (P[i] & C[i]);
			assign S[i] = P[i] ^ C[i];
		end
	endgenerate

	assign CO = C[4];
endmodule