题解 | #异步复位同步释放#

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
reg a1;
reg a2;
wire rst_o;
always@(posedge clk or negedge rst_n)
begin if(!rst_n)
    {a2,a1}<=0;
    else {a2,a1}<={a1,1'b1};
end
assign rst_o=a2;
always@(posedge clk or negedge rst_o)
begin if(!rst_o)
dout<=0;
else dout<=d;
end
    
//*************code***********//
endmodule