题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	reg [3:0]next_state;
	reg [3:0]cur_state;
	parameter ST0=4'b0000;
	parameter ST1=4'b0001;
	parameter ST2=4'b0010;
	parameter ST3=4'b0011;
	parameter ST4=4'b0100;
	parameter ST5=4'b0101;
	parameter FT1=4'b0111;
	parameter FT2=4'b1000;
	parameter FT3=4'b1001;
	parameter FT4=4'b1010;
	parameter FT5=4'b1011;
	parameter OT1=4'b1100;//符合序列状态
	parameter WT1=4'b1101;//不符合序列状态
	//状态转移
	always@(posedge clk or negedge rst_n)
	begin
	   if(~rst_n)
	      cur_state<=ST0;
	   else
		  cur_state<=next_state;
	end
	//match输出
	always@(posedge clk or negedge rst_n)
	if(~rst_n)
	begin
		match<=0;
		not_match<=0;
	end
	else
	begin
	/*
	↓↓↓下面如果用cur_state，结果会比答案要求延时一个时钟周期，
	*/
		match<=(next_state==OT1);
		not_match<=(next_state==WT1);
	end
	//状态转移逻辑
	always@(cur_state or data)
	begin
		case(cur_state)
		ST0:next_state<=(data?FT1:ST1);
		ST1:next_state<=(data?ST2:FT2);
		ST2:next_state<=(data?ST3:FT3);
		ST3:next_state<=(data?ST4:FT4);
		ST4:next_state<=(data?FT5:ST5);
		ST5:next_state<=(data?WT1:OT1);
		FT1:next_state<=FT2;
		FT2:next_state<=FT3;
		FT3:next_state<=FT4;
		FT4:next_state<=FT5;
		FT5:next_state<=WT1; 
		OT1:next_state<=(data?FT1:ST1);
		WT1:next_state<=(data?FT1:ST1);
		endcase
	end
endmodule