题解 | #Johnson Counter#

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);

//三段式状态机实现

reg [3:0] cur_state, next_state;
parameter st0 = 4'b0000;
parameter st1 = 4'b1000;
parameter st2 = 4'b1100;
parameter st3 = 4'b1110;
parameter st4 = 4'b1111;
parameter st5 = 4'b0111;
parameter st6 = 4'b0011;
parameter st7 = 4'b0001;

always@(posedge clk or negedge rst_n)  begin
    if(!rst_n)
        cur_state <= st0;
    else
        cur_state <= next_state;
end

always@(*)  begin
    case(cur_state)
        st0: next_state <= st1;
        st1: next_state <= st2;
        st2: next_state <= st3;
        st3: next_state <= st4;
        st4: next_state <= st5;
        st5: next_state <= st6;
        st6: next_state <= st7;
        st7: next_state <= st0;
        default: next_state <= st0;
    endcase
end

always@(posedge clk or negedge rst_n)  begin
    if(!rst_n)
        Q <= 'd0;
    else
        Q <= next_state;
end
endmodule