题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//

reg [2:0] q;

always@(posedge clk_in,negedge rst)  begin
    if(rst==1'b0) q[0] <=0;
    else q[0] <= ~q[0];
end

always@(posedge q[0],negedge rst)  begin
    if(rst==1'b0) q[1] <= 0;
    else q[1] <= ~q[1];
end

always@(posedge q[1],negedge rst)  begin
    if(rst==1'b0) q[2] <=0;
    else q[2] <= ~q[2];
end

assign {clk_out8,clk_out4,clk_out2} = q;
//*************code***********//
endmodule