题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);

reg [3:0] rom_data [7:0];
reg [3:0] temp_data;

assign data = temp_data;
//保持rom中的数据不变
always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		begin
			rom_data[0] <= 4'd0;
			rom_data[1] <= 4'd2;
			rom_data[2] <= 4'd4;
			rom_data[3] <= 4'd6;
			rom_data[4] <= 4'd8;
			rom_data[5] <= 4'd10;
			rom_data[6] <= 4'd12;
			rom_data[7] <= 4'd14;
		end
	else
		begin
			rom_data[0] <= 4'd0;
			rom_data[1] <= 4'd2;
			rom_data[2] <= 4'd4;
			rom_data[3] <= 4'd6;
			rom_data[4] <= 4'd8;
			rom_data[5] <= 4'd10;
			rom_data[6] <= 4'd12;
			rom_data[7] <= 4'd14;
		end
end

always@(*)(1444584) //这个地方如果用clk的上升沿会不通过，clk的上升沿和下降沿都需要更新data中的数据
begin
	if(!rst_n)
		temp_data <= 4'd0;
	else
		temp_data <= rom_data[addr];
end
endmodule