题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
//寄存器
reg a_reg;

//d触发器
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		a_reg <= 0;
	else
		a_reg <= a;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		rise <= 0;
		down <= 0;
	end
	if(a==0 && a_reg==1)begin
		down <= 1;
		rise <= 0;
	end
	else if(a==1 && a_reg==0)begin
		rise <= 1;
		down <= 0;
	end
	else begin
		down <= 0;
		rise <= 0;
	end
end	
endmodule