题解 | #含有无关项的序列检测#相对复杂的状态机处理方法

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
);
parameter IDLE = 1'b0,S1 = 1'b1,S2 = 2'b10,S3 = 2'b11;
parameter SX_1  = 3'b100,SX_2  = 3'b101,SX_3  = 3'b110;
reg [2:0] current_state,next_state;
reg match_change;

//
always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    current_state <= IDLE;
  else
    current_state <= next_state;
end

//根据是否检查完中间的无关项来判断状态机的循环状态
//复用了前面的状态机
always@(*)begin
  if(!match_change)begin
	case(current_state)
	  IDLE:next_state = a?IDLE:S1;
	  S1:next_state = a?S2:S1;
	  S2:next_state = a?S3:S1;
	  S3:next_state = a?SX_1:SX_1;
	  SX_1:next_state = a?SX_2:SX_2;
	  SX_2:next_state = a?SX_3:SX_3;
	  SX_3:next_state = a?S1:IDLE;
	  default:next_state = next_state;
	endcase
  end
  else begin
	case(current_state)
	S1 :next_state = a?S2:IDLE;
	S2 :next_state = a?IDLE:S3;
	S3 :next_state = a?IDLE:IDLE;
	endcase
  end
end

//为了拍子不乱用了组合逻辑电路
always@(*)begin
  if(!rst_n)
    match_change = 1'b0;
  else if((current_state == SX_3)&&(next_state == S1))
    match_change = 1'b1;
  else if(current_state == IDLE)
    match_change = 1'b0;
  else
    match_change = match_change;
end

//三段式状态机的输出最好用时序逻辑电路
//判断条件使用current_state还是next_state取决于你的设置的状态机状态个数
//如果状态个数正好，就需要用next_state,如果有一个冗余，就可以用current_state
always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
   match <= 1'b0;
  else if((current_state == S3)&&(match_change == 1'b1))
   match <= 1'b1;
  else
   match <= 1'b0;
end
  
endmodule