题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg dff0,dff1,dff2;
always@(posedge clk_in or negedge rst) begin
    if(!rst) begin
        dff0 <= 0;
    end
    else begin
        dff0 <= ~dff0;
    end
end
always@(posedge dff0 or negedge rst) begin
    if(!rst) begin
        dff1 <= 0;
    end
    else begin
        dff1 <= ~dff1;
    end
end
always@(posedge dff1 or negedge rst) begin
    if(!rst) begin
        dff2 <= 0;
    end
    else begin
        dff2 <= ~dff2;
    end
end
assign clk_out2 = dff0,
        clk_out4 = dff1,
        clk_out8 = dff2;
//*************code***********//
endmodule