题解 | #优先编码器Ⅰ#

always 里面过程赋值要用reg；连续赋值assign用wire。

怎么感觉这个写得这么蠢啊hhhh

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);

reg [2:0]Y_temp;
reg GS_temp;
reg EO_temp;

always @(*)(1444584)
begin
    if (EI == 0)
    begin
        Y_temp = 3'b000;
        GS_temp = 0;
        EO_temp = 0;
    end
    else 
    casex(I)
    8'b00000000: begin 
        Y_temp = 3'b000;
        GS_temp = 0;
        EO_temp = 1; end
    8'b1xxxxxxx: begin 
        Y_temp = 3'b111;
        GS_temp = 1;
        EO_temp = 0; end
    8'b01xxxxxx: begin 
        Y_temp = 3'b110;
        GS_temp = 1;
        EO_temp = 0; end   
    8'b001xxxxx:  begin 
        Y_temp = 3'b101;
        GS_temp = 1;
        EO_temp = 0; end
    8'b0001xxxx:  begin
        Y_temp = 3'b100;
        GS_temp = 1;
        EO_temp = 0; end
    8'b00001xxx:  begin
        Y_temp = 3'b011;
        GS_temp = 1;
        EO_temp = 0; end
    8'b000001xx:  begin
        Y_temp = 3'b010;
        GS_temp = 1;
        EO_temp = 0; end
    8'b0000001x:  begin
        Y_temp = 3'b001;
        GS_temp = 1;
        EO_temp = 0; end
    8'b00100001:  begin
        Y_temp = 3'b000;
        GS_temp = 1;
        EO_temp = 0; end
    default: begin 
        Y_temp = 3'b000;
        GS_temp = 0;
        EO_temp = 0; end
    endcase
end
    
assign Y =  Y_temp;
assign GS = GS_temp;
assign EO = EO_temp;

endmodule