题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

	parameter IDEL=0, S0=1, S1=2, S2=3;
	reg [1:0] cstate, nstate;

	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cstate <= IDEL;
		end
		else begin
			cstate <= nstate;
		end
	end

	always@(*) begin
		case(cstate)
			IDEL:   nstate = data_valid?(data?IDEL:S0):cstate;
			S0:		nstate = data_valid?(data?S1:S0):cstate;
			S1:		nstate = data_valid?(data?S2:S0):cstate;
			S2:		nstate = data_valid?IDEL:cstate;
			default:nstate = IDEL;
		endcase
	end

	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			match <= 1'b0;
		end
		else begin
			match <= (cstate==S2) & data_valid & (~data);
		end
	end
  
endmodule