题解 | #输入序列连续的序列检测#
输入序列连续的序列检测
https://www.nowcoder.com/practice/d65c2204fae944d2a6d9a3b32aa37b39
本题的序列检测很明显可以采用状态机进行检测，在检测时可以选取一位一位的状态机检测，也可以采取分段的方式进行检测，这样就能做到对状态机的简化 `timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); // localparam IDEL_state = 8'b0000_0001; // localparam One_state = 8'b0000_0010; // localparam Two_state = 8'b0000_0100; // localparam Thre_state = 8'b0000_1000; // localparam Four_state = 8'b0001_0000; // localparam Five_state = 8'b0010_0000; // localparam Six_state = 8'b0100_0000; // localparam Seve_state = 8'b1000_0000; localparam IDEL_state = 2'b00; localparam One_state = 2'b01; localparam Two_state = 2'b10; localparam Thre_state = 2'b11; reg match_reg; reg [1:0] one_cnt; reg [1:0] zero_cnt; // reg [7:0] cur_state; // reg [7:0] nex_state; reg [1:0] cur_state; reg [1:0] nex_state; reg skip_en; reg skip_waite; reg skip_break; // always@(posedge clk or negedge rst_n) // begin // if(!rst_n) // cur_state <= 8'b0; // else // cur_state <= nex_state; // end // always@(*) // begin // nex_state = IDEL_state; // case(cur_state) // IDEL_state : begin // if(skip_en) // nex_state = One_state; // else // nex_state = IDEL_state; // end // One_state : begin // if(skip_en) // nex_state = Two_state; // else // nex_state = IDEL_state; // end // Two_state : begin // if(skip_en) // nex_state = Thre_state; // else // nex_state = IDEL_state; // end // Thre_state : begin // if(skip_en) // nex_state = Four_state; // else // nex_state = IDEL_state; // end // Four_state : begin // if(skip_en) // nex_state = Five_state; // else // nex_state = IDEL_state; // end // Five_state : begin // if(skip_en) // nex_state = Six_state; // else // nex_state = IDEL_state; // end // Six_state : begin // if(skip_en) // nex_state = Seve_state; // else // nex_state = IDEL_state; // end // Seve_state : begin // if(skip_en) // nex_state = IDEL_state; // else // nex_state = IDEL_state; // end // default : begin // nex_state = IDEL_state; // end // endcase // end // always@(posedge clk or negedge rst_n) // begin // if(!rst_n) // begin // match_reg <= 1'b0; // skip_en <= 1'b0; // end // else // begin // skip_en <= 1'b0; // case(nex_state) // IDEL_state : begin // match_reg <= 1'b0; // if(a == 1'b0) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // One_state : begin // match_reg <= 1'b0; // if(a == 1'b1) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Two_state : begin // match_reg <= 1'b0; // if(a == 1'b1) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Thre_state : begin // match_reg <= 1'b0; // if(a == 1'b1) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Four_state : begin // match_reg <= 1'b0; // if(a == 1'b0) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Five_state : begin // match_reg <= 1'b0; // if(a == 1'b0) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Six_state : begin // match_reg <= 1'b0; // if(a == 1'b0) // skip_en <= 1'b1; // else // skip_en <= 1'b0; // end // Seve_state : begin // if(a == 1'b1) // begin // skip_en <= 1'b1; // match_reg <= 1'b1; // end // else // begin // skip_en <= 1'b0; // match_reg <= 1'b0; // end // end // default : match_reg <= 1'b0; // endcase // end // end always@(posedge clk or negedge rst_n) begin if(!rst_n) cur_state <= 2'b0; else cur_state <= nex_state; end always@(*) begin nex_state = IDEL_state; case(cur_state) IDEL_state : begin if(skip_en) nex_state = One_state; else if(skip_break) nex_state = IDEL_state; else nex_state = IDEL_state; end One_state : begin if(skip_en) nex_state = Two_state; else if(skip_waite) nex_state = One_state; else if(skip_break) nex_state = IDEL_state; else nex_state = One_state; end Two_state : begin if(skip_en) nex_state = Thre_state; else if(skip_waite) nex_state = Two_state; else if(skip_break) nex_state = IDEL_state; else nex_state = Two_state; end Thre_state : begin if(skip_en) nex_state = IDEL_state; else if(skip_break) nex_state = IDEL_state; else nex_state = Thre_state; end default : begin nex_state = IDEL_state; end endcase end always@(posedge clk or negedge rst_n) begin if(!rst_n) begin match_reg <= 1'b0; skip_en <= 1'b0; skip_waite <= 1'b0; skip_break <= 1'b0; one_cnt <= 2'b0; zero_cnt <= 2'b0; end else begin skip_waite <= 1'b0; skip_en <= 1'b0; skip_break <= 1'b0; case(nex_state) IDEL_state : begin match_reg <= 1'b0; if(a == 1'b0) skip_en <= 1'b1; else skip_break <= 1'b1; end One_state : begin match_reg <= 1'b0; if(a == 1'b1) begin if(one_cnt == 2'd2) begin one_cnt <= 2'b0; skip_en <= 1'b1; skip_waite <= 1'b0; skip_break <= 1'b0; end else begin one_cnt <= one_cnt + 1'b1; skip_waite <= 1'b1; skip_break <= 1'b0; end end else begin one_cnt <= 2'b0; skip_en <= 1'b0; skip_waite <= 1'b0; skip_break <= 1'b1; end end Two_state : begin match_reg <= 1'b0; if(a == 1'b0) begin if(zero_cnt == 2'd2) begin zero_cnt <= 2'b0; skip_en <= 1'b1; skip_waite <= 1'b0; skip_break <= 1'b0; end else begin zero_cnt <= zero_cnt + 1'b1; skip_waite <= 1'b1; skip_break <= 1'b0; end end else begin zero_cnt <= 2'b0; skip_en <= 1'b0; skip_waite <= 1'b0; skip_break <= 1'b1; end end Thre_state : begin if(a == 1'b1) begin skip_en <= 1'b1; match_reg <= 1'b1; skip_break <= 1'b1; end else begin skip_en <= 1'b0; match_reg <= 1'b0; skip_break <= 1'b1; end end default : match_reg <= 1'b0; endcase end end always@(posedge clk or negedge rst_n) begin if(!rst_n) match <= 1'b0; else match <= match_reg; end endmodule
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