题解 | #优先编码器Ⅰ#

优先编码器Ⅰ

https://www.nowcoder.com/practice/a7068b8f4c824d6a9592f691990b21de

对照真值表，直接用casex解决是一个很简便的方法，在消耗资源上也不会比其他方法更多。

当然，直接根据真值表写逻辑表达式再按与非关系转换也是可以的。

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);


reg [2:0] Yreg;
reg GSreg,EOreg;
assign Y = Yreg;
assign GS = GSreg;
assign EO = EOreg;
    
always@(EI or I or Yreg or GSreg or EOreg)
    begin
        if(!EI)
            begin
                Yreg = 0;
                GSreg = 0;
                EOreg = 0;
            end
        else
            begin
                casex(I)
                    8'b0000_0000: begin
                        Yreg = 0;
                        GSreg = 0 ;
                        EOreg = 1;
                    end
                    8'b1xxx_xxxx: begin
                        Yreg = 3'b111;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b01xx_xxxx: begin
                        Yreg = 3'b110;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b001x_xxxx: begin
                        Yreg = 3'b101;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b0001_xxxx: begin
                        Yreg = 3'b100;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b0000_1xxx: begin
                        Yreg = 3'b011;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b0000_01xx: begin
                        Yreg = 3'b010;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b0000_001x: begin
                        Yreg = 3'b001;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                    8'b0000_0001: begin
                        Yreg = 3'b000;
                        GSreg = 1 ;
                        EOreg = 0 ;
                    end
                endcase
            end
    end
    
    endmodule