题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input a,
    output reg match
    );
    reg [8:0] match_temp;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            match_temp <= 9'b0;
        else
            match_temp <= {match_temp[7:0],a};
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            match <= 1'b0;
        else if(match_temp[8:6] == 3'b011 && match_temp[2:0] == 3'b110)
            match <= 1'b1;
        else
            match <= 1'b0;
    end
endmodule