题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p( input clk ,
input rst_n , input valid_a , input data_a ,

output	reg 		ready_a		,
output	reg			valid_b		,
output  reg [5:0] 	data_b

);

reg [2:0] cnt;

reg [5:0] data_bb;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt<=3'b0;
    else if (valid_a)
        if (cnt==3'd5)
            cnt<=3'd0;
        else
        cnt<=cnt+1'd1;
    else
        cnt<=cnt;
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        valid_b<=1'b0;
    else if (cnt==3'd5)
        valid_b<=1'b1;
    else
        valid_b<=1'b0;
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        data_bb<=5'b0;
    else if ((cnt==3'd0)&&valid_a)
        data_bb[0]<=data_a;
    else if ((cnt==3'd1)&&valid_a)
        data_bb[1]<=data_a;
    else if ((cnt==3'd2)&&valid_a)
        data_bb[2]<=data_a;
    else if ((cnt==3'd3)&&valid_a)
        data_bb[3]<=data_a;
    else if ((cnt==3'd4)&&valid_a)
        data_bb[4]<=data_a;
    else if ((cnt==3'd5)&&valid_a)
        data_bb[5]<=data_a;
    else
        data_bb<=data_bb;
end
 
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        data_b<=5'b0;
    else if (cnt==3'd5)
        data_b<=data_bb;
    else
        data_b<=data_b;
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        ready_a<=1'b0;
    else
        ready_a<=1'b1;
end

endmodule