题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL( input clk, input rst_n, input data_in, output reg data_out );

reg data_in_reg;
wire data_and;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        data_in_reg <= 0;
        data_out <= 0;
    end
    else begin
        data_in_reg <= data_in;
        data_out <= data_and;
    end
end

assign data_and = data_in & (~data_in_reg);

endmodule