题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    reg[3:0]cnt;
    reg[143:0]data_reg;
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)begin
            cnt<='d0;
        end
        else if(valid_in)begin
            cnt<=cnt+1;             /*    加到4'd15后再加1变成4'd0   */
        end
        else begin
            cnt<=cnt;
        end
    end
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)begin
            valid_out<=1'b0;
        end
        else if(cnt==4'd5||cnt==4'd10||cnt==4'd15)begin
            valid_out<=1'b1;
        end
        else begin
            valid_out<=1'b0;
        end
    end
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)begin
            data_reg<='b0;
        end
        else if(valid_in)begin
            data_reg<={data_reg[119:0],data_in};
        end
        else begin
            data_reg<=data_reg;
        end
    end
    always@(posedge clk&nbs***bsp;negedge rst_n)begin
        if(!rst_n)begin
            data_out<='b0;
        end
        else if(cnt==4'd5)begin
            data_out<={data_reg[119:0],data_in[23:16]};
        end
        else if(cnt==4'd10)begin
            data_out<={data_reg[111:0],data_in[23:8]};
        end
        else if(cnt==4'd15)begin
            data_out<={data_reg[103:0],data_in};
        end
        else begin
            data_out<=data_out;
        end
    end
        
               
endmodule