题解 | 边沿检测

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a1;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		a1   <= 0;
		rise <= 0;
		down <= 0;
	end else begin
		a1   <= a;
		if(a & (~a1)) begin
			rise <= 1'b1;
		end else begin
			rise <= 1'b0;
		end

		if((~a) & a1) begin
			down <= 1'b1;
		end else begin
			down <= 1'b0;
		end
	end
end	

endmodule