题解 | 任意奇数倍时钟分频

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
    reg [2:0]cntp;
	reg [2:0]cntn;
	reg clk_out_p;
	reg clk_out_n;

//上升沿计数
always @(posedge clk_in or negedge rst_n)begin
if(!rst_n)begin
cntp <= 3'b0;
end
else begin
  if(cntp == dividor-1) cntp <= 3'b0; 
  else cntp <= cntp +1'd1;
end
end

//上升沿分频
always @(posedge clk_in or negedge rst_n)begin
if(!rst_n)begin
clk_out_p <= 1'b0;
end
else begin
	if( cntp == (dividor-1)/2 || cntp == dividor-1) clk_out_p <= ~clk_out_p;
	else clk_out_p <= clk_out_p;
end
end

//下降沿计数
always @(negedge clk_in or negedge rst_n)begin
if(!rst_n)begin
cntn <= 3'b0;
end
else begin
  if(cntn == dividor-1) cntn <= 3'b0; 
  else cntn <= cntn +1'd1;
end
end

//下降沿分频
always @(negedge clk_in or negedge rst_n)begin
if(!rst_n)begin
clk_out_n <= 1'b0;
end
else begin
	if( cntn == (dividor-1)/2 || cntn == dividor-1) clk_out_n <= ~clk_out_n;
	else clk_out_n <= clk_out_n;
end
end

assign clk_out = clk_out_p | clk_out_n;

endmodule

`timescale 1ns/1ns

module tb_clk_divider;

    reg clk_in;
    reg rst_n;
    wire clk_out;

    // 例化待测模块
    clk_divider #(
        .dividor(5)
    ) uut (
        .clk_in  (clk_in),
        .rst_n   (rst_n),
        .clk_out (clk_out)
    );

    // 产生输入时钟：周期 10ns
    initial begin
        clk_in = 1'b0;
        forever #5 clk_in = ~clk_in;
    end

    // 复位与激励
    initial begin
        rst_n = 1'b0;
        #22;
        rst_n = 1'b1;

        #300;
        $stop;
    end

    // 生成波形文件
    initial begin
        $dumpfile("tb_clk_divider.vcd");
        $dumpvars(0, tb_clk_divider);
    end

endmodule

仿真没问题 不知道为啥在牛客上面就是过不了？