题解 | 异步FIFO

`timescale 1ns/1ns

/***************************************RAM*****************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/***************************************AFIFO*****************************************/
module asyn_fifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					wclk	, 
	input 					rclk	,   
	input 					wrstn	,
	input					rrstn	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output wire				wfull	,
	output wire				rempty	,
	output wire [WIDTH-1:0]	rdata
);
    
wire wenc;
wire renc;
wire [$clog2(DEPTH)-1:0] waddr;     //读写地址
wire [$clog2(DEPTH)-1:0] raddr;
reg  [$clog2(DEPTH):0]   waddr_pro; //读写指针
reg  [$clog2(DEPTH):0]   raddr_pro;
wire [$clog2(DEPTH):0]   waddr_gray;//格雷码
wire [$clog2(DEPTH):0]   raddr_gray;
reg  [$clog2(DEPTH):0]   waddr_gray_w1;
reg  [$clog2(DEPTH):0]   raddr_gray_r1;
reg  [$clog2(DEPTH):0]   waddr_gray_r2;//格雷码二级同步
reg  [$clog2(DEPTH):0]   waddr_gray_r3;
reg  [$clog2(DEPTH):0]   raddr_gray_w2;
reg  [$clog2(DEPTH):0]   raddr_gray_w3;

assign wenc = winc & !wfull;
assign renc = rinc & !rempty;

always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)begin
        waddr_pro <= 'd0;
    end
    else if(wenc) begin
        waddr_pro <= waddr_pro + 1;
    end
end

always@(posedge rclk or negedge rrstn)begin
    if(!rrstn)begin
        raddr_pro <= 'd0;
    end
    else if(renc) begin
        raddr_pro <= raddr_pro + 1;
    end
end

always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)begin
        waddr_gray_w1 <= 'd0;
    end
    else begin
        waddr_gray_w1 <= waddr_gray;
    end
end
always@(posedge rclk or negedge rrstn)begin
    if(!rrstn)begin
        waddr_gray_r2 <= 'd0;
        waddr_gray_r3 <= 'd0;
    end
    else begin
        waddr_gray_r2 <= waddr_gray_w1;
        waddr_gray_r3 <= waddr_gray_r2;
    end
end

always@(posedge rclk or negedge rrstn)begin
    if(!rrstn)begin
        raddr_gray_r1 <='d0;
    end
    else begin
        raddr_gray_r1 <= raddr_gray;
    end
end
always@(posedge wclk or negedge wrstn)begin
    if(!wrstn)begin
        raddr_gray_w2 <= 'd0;
        raddr_gray_w3 <= 'd0;
    end
    else begin
        raddr_gray_w2 <= raddr_gray_r1;
        raddr_gray_w3 <= raddr_gray_w2;
    end
end
//地址
assign waddr = waddr_pro[$clog2(DEPTH)-1:0];
assign raddr = raddr_pro[$clog2(DEPTH)-1:0];
//二进制转格雷码
assign waddr_gray = waddr_pro ^ (waddr_pro>>1);
assign raddr_gray = raddr_pro ^ (raddr_pro>>1);
//空满信号
assign wfull = (waddr_gray_w1=={~raddr_gray_w3[$clog2(DEPTH):$clog2(DEPTH)-1],raddr_gray_w3[$clog2(DEPTH)-2:0]});
assign rempty = (raddr_gray_r1==waddr_gray_r3);

    
    dual_port_RAM #(
        .DEPTH(DEPTH),
        .WIDTH(WIDTH)
    )
    myRAM(
        .wclk (wclk ),
        .wenc (wenc ),
        .waddr(waddr),
        .wdata(wdata),
        .rclk (rclk ),
        .renc (renc ),
        .raddr(raddr),
        .rdata(rdata)
    );
endmodule