题解 | 信号发生器

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);

	reg [4:0] cnt_square; // 方波计数器 
	reg dir;              // 三角波方向标志 
 
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            cnt_square <= 'd0;
        end
        else if(wave_choise=='d0)begin
            if(cnt_square >= 'd19) begin
                cnt_square <= 'd0;
            end
            else begin
                cnt_square <= cnt_square +1;
            end
        end
        else begin
            cnt_square <= 'd0;
        end
    end

    always @(*) begin
        if(wave_choise=='d2)begin
            if (wave>='d20)
                dir<=0;
            else if (wave==0)
                dir<=1;
		end
        else begin
            if(wave=='d0)
                dir<=1;
            else 
                dir<=0;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            wave <= 'd0;
        end
        else begin
            if(wave_choise=='d0)begin
                wave = (cnt_square<'d9)? 'd0: 
                        (cnt_square<'d19)? 'd20:'d0;
            end
            else if(wave_choise=='d1)begin
                wave = (wave>='d20)? 'd0: wave+1;
            end
            else if(wave_choise=='d2)begin
                wave = dir? wave+1:wave-1;
            end
            else begin
                wave <= 'd0;
            end
        end
    end
  
endmodule