题解 | 根据状态转移写状态机-三段式

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//通过状态转移图可以看出，输出由当前状态和输入共同决定-->mealy机
reg [1:0] current_state,next_state;

always@(posedge clk or negedge rst)
if(!rst)
  current_state <= 2'd0;
else
  current_state <= next_state;

always@(*)
  case(current_state)
  2'd0:next_state = data ? 2'd1 :2'd0;
  2'd1:next_state = data ? 2'd2 :2'd1;
  2'd2:next_state = data ? 2'd3 :2'd2;
  2'd3:next_state = data ? 2'd0 :2'd3;
  default:next_state = 2'd0;
  endcase

always@(posedge clk or negedge rst)
if(!rst)
  flag <= 0;
else if(current_state==2'd3 && data)
  flag <= 1;
else
  flag <= 0;
//*************code***********//
endmodule