题解 | 移位运算与乘法

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [2:0]current_state;
reg [2:0]next_state;
reg [7:0]d_reg;
//三段式状态机
always@(posedge clk or negedge rst)begin
    if(!rst)
        current_state <= 3'd000;
    else 
        current_state <= next_state;
end
always@(*)begin
    case(current_state)
        3'd000: begin  
            next_state <= 3'd001;
        end
        3'd001: begin
            next_state <= 3'd002;
        end
        3'd002: begin
            next_state <= 3'd003;
        end
        3'd003: begin
            next_state <= 3'd004;
        end
        3'd004: begin
            next_state <= 3'd001;
        end
        default: begin
            next_state <= 3'd000;
        end
    endcase
end
always@(posedge clk or negedge rst)begin
if(!rst) begin
    d_reg <= 0;
    input_grant <= 'd0;
    out <= 'd0; 
end
else begin   
    case(next_state)
        3'd000: begin
            d_reg <= 0;
            input_grant <= 'd0;
            out <= 'd0; 
        end
        3'd001: begin
            d_reg <= d;
            input_grant <= 'd1;
            out <= d; 
        end
        3'd002: begin
            d_reg <= d_reg;
            input_grant <= 'd0;
            out <= (d_reg<<1) + d_reg; 
        end
        3'd003: begin
            d_reg <= d_reg;
            input_grant <= 'd0;
            out <= (d_reg<<3) - d_reg; 
        end
        3'd004: begin
            d_reg <= d_reg;
            input_grant <= 'd0;
            out <= (d_reg<<3) ; 
        end
        default: begin
            d_reg <= 'd0;
            input_grant <= 'd0;
            out <= 'd0 ; 
        end
    endcase
end
end
//*************code***********//
endmodule