`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
parameter S0=0,S05=1,S10=2,S15=3,S20=4,S25=5,S30=6;
reg [2:0]state,next;
always@(posedge clk or negedge rst)
if (~rst)
state <= S0;
else
state <= next;
always@(*)
if (~rst)
next = S0;
else case(state)
S0 : next = {d1,d2,d3}==3'b100 ? S05: //0 //0.5 1.0 2.0
{d1,d2,d3}==3'b010 ? S10:
{d1,d2,d3}==3'b001 ? S20: next;
S05: next = {d1,d2,d3}==3'b100 ? S10: //0.5
{d1,d2,d3}==3'b010 ? S15:
{d1,d2,d3}==3'b001 ? S25: next;
S10: next = {d1,d2,d3}==3'b100 ? S15: //1.0
{d1,d2,d3}==3'b010 ? S20:
{d1,d2,d3}==3'b001 ? S30: next;
S15: next = {d1,d2,d3}==3'b100 ? S05: //1.5
{d1,d2,d3}==3'b010 ? S10:
{d1,d2,d3}==3'b001 ? S20: S0;
S20: next = {d1,d2,d3}==3'b100 ? S05: //2.0
{d1,d2,d3}==3'b010 ? S10:
{d1,d2,d3}==3'b001 ? S20: S0;
S25: next = {d1,d2,d3}==3'b100 ? S05: //2.5
{d1,d2,d3}==3'b010 ? S10:
{d1,d2,d3}==3'b001 ? S20: S0;
S30: next = {d1,d2,d3}==3'b100 ? S05: //3.0
{d1,d2,d3}==3'b010 ? S10:
{d1,d2,d3}==3'b001 ? S20: S0;
default: next = S0;
endcase
always@(posedge clk or negedge rst)
if (~rst) begin
out1 <= 1'b0;
out2 <= 2'd0;
end
else begin
case (next)
S15:begin out1 <= 1'b1; out2 <= 2'd0; end
S20:begin out1 <= 1'b1; out2 <= 2'd1; end
S25:begin out1 <= 1'b1; out2 <= 2'd2; end
S30:begin out1 <= 1'b1; out2 <= 2'd3; end
default: begin out1 <= 1'b0; out2 <= 2'd0; end
endcase
end
//*************code***********//
endmodule