题解 | 位拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//

reg [15:0] d_reg;
always@(posedge clk or negedge rst)
    if (~rst) begin
        out <= 0;
        validout <=0;
        d_reg<=0;
    end else if (sel==2'b00) begin
        d_reg<=d;
    end

always@(*)begin
    case(sel)
    2'b00:begin out = 0                         ; validout = 1'b0; end
    2'b01:begin out = d_reg[3:0] + d_reg[7:4]   ; validout = 1'b1; end
    2'b10:begin out = d_reg[3:0] + d_reg[11:8]  ; validout = 1'b1; end
    2'b11:begin out = d_reg[3:0] + d_reg[15:12] ; validout = 1'b1; end
    default:begin out = 0                         ; validout = 1'b0; end
    endcase
end




//*************code***********//
endmodule