题解 | 输入序列连续的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [3:0] r_st_current, r_st_next;

localparam P_IDLE = 4'd0, 
		   P_S1   = 4'd1,
		   P_S2   = 4'd2,
		   P_S3   = 4'd3,
		   P_S4   = 4'd4,
		   P_S5   = 4'd5,
		   P_S6   = 4'd6,
		   P_S7   = 4'd7,
		   P_S8   = 4'd8;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)
		r_st_current <= P_IDLE;
	else
		r_st_current <= r_st_next;
end		 
 always@(*)begin
	if(!rst_n)
		r_st_next <= P_IDLE;
	else begin
		case(r_st_current)
			P_IDLE : r_st_next <= a? P_IDLE	: P_S1;
			P_S1   : r_st_next <= a? P_S2	: P_S1;
			P_S2   : r_st_next <= a? P_S3	: P_S1;
			P_S3   : r_st_next <= a? P_S4	: P_S1;
			P_S4   : r_st_next <= a? P_IDLE	: P_S5;
			P_S5   : r_st_next <= a? P_S2	: P_S6;
			P_S6   : r_st_next <= a? P_S2	: P_S7;
			P_S7   : r_st_next <= a? P_S8	: P_S1;
			P_S8   : r_st_next <= a? P_S3	: P_S1;
			default: r_st_next <= P_IDLE;
		endcase

	end
 end
always@(posedge clk, negedge rst_n)begin
	if(!rst_n)
		match <= 1'b0;
	else if(r_st_current == P_S8)
		match <= 1'b1;
	else 
		match <= 1'b0;
end		 
  
endmodule