题解 | #输入序列连续的序列检测#

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

    reg [7:0] target = 8'b011_100_01;
    reg [7:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            match <= 0;
            shift_reg <= 8'b000_000_00;
        end else begin
            shift_reg <= {shift_reg[6:0], a};
            match <= shift_reg == target;
        end
    end
endmodule