题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
localparam        S0       =        2'b00           ,
                  S1       =        2'b01           ,
                  S2       =        2'b10           ,
                  S3       =        2'b11           ;      

reg     [1:0]               current_state           ;
reg     [1:0]               next_state              ;

always@(posedge clk, negedge rst_n)begin
    if(!rst_n)
        current_state          <=           'd0     ;
    else
        current_state          <=           next_state;
end

always@(*)begin
    case(current_state)
        S0:begin
            if(C)
                next_state      <=         S1       ;
            else
                next_state      <=          S0      ;
        end
        S1:begin
            if(C)
                next_state      <=         S1       ;
            else
                next_state      <=         S3      ;
        end
        S2:begin
            if(C)
                next_state      <=         S2       ;
            else
                next_state      <=         S0      ;
        end
        S3:begin
            if(C)
                next_state      <=         S2       ;
            else
                next_state      <=         S3      ;
        end
    endcase
end

assign   Y = (((current_state == S3)&&(next_state == S3) && ~C) || ((next_state == S2) && C))?1'b1:1'b0;

endmodule