题解 | #多功能数据处理器#

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		c<='d0;
	end
	else begin
		case(select)
			'd0:c<=a;
			'd1:c<=b;
			'd2:c<=a+b;
			'd3:c<=a-b;
			default:c<='d0;


		endcase


	end



end





















endmodule