题解 | #奇偶校验#

`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//
wire    w_temp,check;
assign w_temp = ^bus[31:0];
assign check = sel=='d1? w_temp:~w_temp;

//*************code***********//
endmodule