题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
reg r_data1;
always@(posedge clk or negedge rst)begin
    if(!rst)begin
        r_data1 <= 'd0;
    end
    else if(data == 'd1)begin
        r_data1 <= ~r_data1;
    end
    else begin
        r_data1 <= r_data1;
    end
end

always@(posedge clk or negedge rst)begin
    if(!rst)begin
        q <= 'd0;
    end
    else if(r_data1 == 'd1)begin
        q <= ~q;
    end
    else begin
        q <= q;
    end
end


//*************code***********//
endmodule