题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0]seq_num;

reg [143:0] data_reg;
 
always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    seq_num <= 1'b0;
  else if(seq_num == 4'd15)
    seq_num <= 1'b0;
  else if(valid_in)
    seq_num <= seq_num + 1'b1;
  else
    seq_num <= seq_num;
end

//取24*6也就是144位作为填充位，其实120位应该就足够了，多余的会直接溢出
always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    data_reg <= 1'b0;
  else if(valid_in)
    data_reg <= {data_reg[119:0],data_in};
end

//除了使用一些寄存器作为缓冲器之外，由于移位寄存器使用时钟触发，再次直接寄存结果会导致结果滞后
//为了使时序与波形一致，data_out不能直接锁存data_reg的值，需要锁存下一时钟周期data_reg的值
//即需要人为的计算该时钟周期下data-reg会寄存的值来寄存
always@(posedge clk or negedge rst_n)begin
  if(!rst_n)begin
    data_out <= 1'b0;
	valid_out <= 1'b0;
  end
  else if(valid_in && (seq_num==3'd5))begin
    data_out <= {data_reg[119:0],data_in[23:16]};
	valid_out <= 1'b1;
  end
  else if(valid_in && (seq_num==4'd10))begin
    data_out <=  {data_reg[111:0], data_in[23:8]};
	valid_out <= 1'b1;
  end
  else if(valid_in && (seq_num==4'd15))begin
    data_out <= {data_reg[103:0], data_in};
	valid_out <= 1'b1;
  end
  else begin
    data_out <= data_out;
	valid_out <= 1'b0;
  end
end

endmodule