题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);

reg [3:0] count;
// reg set_reg;

// always @(posedge clk or negedge rst_n)begin
// 	if(!rst_n)begin
// 		set_reg <= 1'b0;
// 	end
// 	else begin
// 		if(set)begin
// 			set_reg <= 1'b1;
// 		end
// 		else begin
// 			set_reg <= 1'b0;
// 		end
// 	end
// end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		count <= 4'b0000;
	end
	else begin
		if(set)begin
			count <= set_num;
		end
		else begin
			count <= count + 1;
		end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		number <= 4'b0000;
	end
	else begin
		number <= count;
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		zero <= 1'b0;
	end
	else begin
		if(count == 4'b0000)begin
			zero <= 1'b1;
		end
		else begin
			zero <= 1'b0;
		end
	end
end

endmodule