题解 | #简易秒表#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			second <= 6'b000000;
		end
		else begin
			if(minute == 60)begin
				second <= 6'b000000;
			end
			else begin
				if(second == 60)begin
					second <= 1;
				end
				else begin
					second <= 1 + second;
				end
			end
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			minute <= 6'b000000;
		end
		else begin
			if(second == 60)begin
				minute <= 1 + minute;
			end
			else begin
				minute <= minute;
			end
		end
	end
	
	
	
endmodule