题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [6:0] next_state;
reg [6:0] current_state;

always @(posedge clk or negedge rst)begin
	if(!rst)begin
		current_state <= 7'b0000001;
	end
	else begin
		current_state <= next_state;
	end
end

always @(posedge clk or negedge rst)begin
	if(!rst)begin
		flag <= 1'b0;
	end
	else begin
		if(next_state == 7'b0100000)begin
			flag <= 1'b1;
		end
		else begin
			flag <= 1'b0;
		end
	end
end

always @(*)begin
	case(current_state)
	7'b0000001:begin
		if(data)begin
			next_state = 7'b0000010;
		end
		else begin
			next_state = 7'b0000001;
		end
	end
	7'b0000010:begin
		if(!data)begin
			next_state = 7'b0000100;
		end
		else begin
			next_state = 7'b0000010;
		end
	end
	7'b0000100:begin
		if(data)begin
			next_state = 7'b0001000;
		end
		else begin
			next_state = 7'b0000001;
		end
	end
	7'b0001000:begin
		if(data)begin
			next_state = 7'b0010000;
		end
		else begin
			next_state = 7'b0000100;
		end
	end
	7'b0010000:begin
		if(data)begin
			next_state = 7'b0100000;
		end
		else begin
			next_state = 7'b0000100;
		end
	end
	7'b0100000:begin
		if(data)begin
			next_state = 7'b1000000;
		end
		else begin
			next_state = 7'b1000000;
		end
	end
	7'b1000000:begin
		next_state = 7'b1000000;
	end
	endcase
end

//*************code***********//
endmodule