题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [1:0] state;
always @(posedge clk or negedge rst)begin
	if(!rst)begin
		state <= 2'b00;
		flag <= 1'b0;
	end
	else begin
		case(state)
		2'b00:begin
			if(data)begin
				state <= 2'b01;
				flag <= 1'b0;
			end
			else begin
				state <= 2'b00;
				flag <= 1'b0;
			end
		end
		2'b01:begin
			if(data)begin
				state <= 2'b10;
				flag <= 1'b0;
			end
			else begin
				state <= 2'b01;
				flag <= 1'b0;
			end
		end
		2'b10:begin
			if(data)begin
				state <= 2'b11;
				flag <= 1'b0;
			end
			else begin
				state <= 2'b10;
				flag <= 1'b0;
			end
		end
		2'b11:begin
			if(data)begin
				state <= 2'b00;
				flag <= 1'b1;
			end
			else begin
				state <= 2'b11;
				flag <= 1'b0;
			end
		end
		endcase
	end
end

//*************code***********//
endmodule