题解 | #状态机-重叠序列检测#

//IC是硬件设计，考虑资源节约，尽量少用额外寄存器
//注意，flag是在条件满足后，打一拍在输出，即S4
//S4中拉高flag后，记得再后续跳转中回低flag信号
`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

reg [2: 0]  state   ;

//state 1011
localparam IDLE = 3'd0;  //000  0000
localparam S1   = 3'd1;  //001  0001
localparam S2   = 3'd2;  //010  0010
localparam S3   = 3'd3;  //101  0101
localparam S4   = 3'd4;  //011  1011


always @(posedge clk or negedge rst)
begin
    if(!rst)  
    begin
        state <= IDLE   ; 
        flag  <= 1'b0   ;
    end
    else
        case(state)
            IDLE:
                state <= state + data   ;
            S1:  //0001
                begin
                    flag  <= 1'b0   ;
                    if(!data)
                        state <= S2     ;
                    else
                        state <= S1     ;     
                end
            S2: //0010
                begin
                    flag  <= 1'b0   ;
                    if(data)
                        state <= S3     ;
                    else
                        state <= IDLE   ;  
                end
            S3: //0101
                begin
                    if(data)
                        state <= S4     ;
                    else
                        state <= S2     ;  
                end
            S4: begin
                flag  <= 1'b1   ;
                if(data)
                    state <= S1 ;
                else
                    state <= S2 ;

            end
        default: state <= IDLE  ;
        endcase
end




endmodule