题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);


reg         cnt ;
reg [7:0]   data_tempt ;

///cnt
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        cnt <= 1'b0 ;
    else if(valid_in)
        cnt <= cnt + 1'b1   ;
end

///data_tempt
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        data_tempt  <= 8'd0 ;
    else if(valid_in)
        data_tempt  <= data_in  ;
end

///valid_out & data_out
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)  begin
        valid_out <= 1'b0   ;
        data_out  <= 16'd0  ;
    end
    else if(cnt == 1'b1 & valid_in) begin
        valid_out <= 1'b1   ;
        data_out  <= {data_tempt,data_in}   ;
    end
    else begin
        valid_out <= 1'b0   ;
        data_out  <= data_out	;
    end
end


endmodule