题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] count1;
reg [2:0] count2;
reg clk_out7_reg1;
reg clk_out7_reg2;

wire clk_out7_wire1;
wire clk_out7_wire2;

assign clk_out7_wire1 = clk_out7_reg1;
assign clk_out7_wire2 = clk_out7_reg2;
assign clk_out7 = clk_out7_wire1 || clk_out7_wire2;

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        count1 <= 0;
    end
    else begin
        if(count1 < 3'b110)begin
            count1 <= count1 + 1;
        end
        else begin
            count1 <= 0;
        end
    end
end

always @(negedge clk_in or negedge rst)begin
    if(!rst)begin
        count2 <= 0;
    end
    else begin
        if(count2 < 3'b110)begin
            count2 <= count2 + 1;
        end
        else begin
            count2 <= 0;
        end
    end
end

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out7_reg1 <= 0;
    end
    else begin
        if(count1 == 3'b011)begin
            clk_out7_reg1 <= ~clk_out7_reg1;
        end
        else if(count1 == 3'b110)begin
            clk_out7_reg1 <= ~clk_out7_reg1;
        end
        else begin
            clk_out7_reg1 <= clk_out7_reg1;
        end
    end
end

always @(negedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out7_reg2 <= 0;
    end
    else begin
        if(count2 == 3'b011)begin
            clk_out7_reg2 <= ~clk_out7_reg2;
        end
        else if(count2 == 3'b110)begin
            clk_out7_reg2 <= ~clk_out7_reg2;
        end
        else begin
            clk_out7_reg2 <= clk_out7_reg2;
        end
    end
end

//*************code***********//
endmodule