题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg [2:0] count;
reg clk_out5_reg;
assign clk_out5 = clk_out5_reg;

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        count <= 0;
    end
    else begin
        if(count < 3'b100)begin
            count <= count + 1;
        end
        else begin
            count <= 0;
        end
    end
end

always @(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out5_reg <= 0;
    end
    else begin
        if(count == 3'b000)begin
            clk_out5_reg <= ~clk_out5_reg;
        end
        else if(count == 3'b010)begin
            clk_out5_reg <= ~clk_out5_reg;
        end
        else begin
            clk_out5_reg <= clk_out5_reg;
        end
    end
end

//*************code***********//
endmodule