题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
reg [2:0] d1_reg;
reg [2:0] d2_reg;
wire [2:0] sum;

always @(posedge d1 or negedge rst)begin
	if(!rst)begin
		d1_reg <= 3'b000;
	end
	else begin
		d1_reg <= d1_reg + 1;
	end
end

always @(posedge d2 or negedge rst)begin
	if(!rst)begin
		d2_reg <= 3'b000;
	end
	else begin
		d2_reg <= d2_reg + 2;
	end
end

always @(posedge out1 or posedge out2)begin
	d1_reg <= 0;
	d2_reg <= 0;
end

assign sum = d1_reg + d2_reg;

always @(posedge clk or negedge rst)begin
	if(!rst)begin
		out1 <= 1'b0;
		out2 <= 1'b0;
		out3 <= 1'b0;
	end
	else begin
		if(!sel)begin
			if(sum >= 3)begin
				out1 <= 1'b1;
				out3 <= sum - 3;
			end
			else begin
				out1 <= 1'b0;
				out3 <= 1'b0;
			end
		end
		else begin
			if(sum >= 5)begin
				out2 <= 1'b1;
				out3 <= sum - 5;
			end
			else begin
				out2 <= 1'b0;
				out3 <= 1'b0;
			end
		end
	end
end


//*************code***********//
endmodule