题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
    input clk,
    input rst_n,
    input valid_in,
    input [7:0] data_in,
    output reg valid_out,
    output reg [15:0] data_out
);

reg [7:0] datain_buff;
reg [1:0] data_count;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        data_count <= 2'b0;
        valid_out <= 1'b0;
        data_out <= 16'b0;
        datain_buff <= 8'b0;
    end else begin
        if (valid_in) begin
            if (data_count == 2'b0) begin
                datain_buff <= data_in; // 缓存第一个8位数据
                data_count <= 2'b1;
                valid_out <= 1'b0;
            end else if (data_count == 2'b1) begin
                data_out <= {datain_buff, data_in}; // 拼接数据
                valid_out <= 1'b1;
                data_count <= 2'b0; // 重置计数器
            end
        end else begin
            valid_out <= 1'b0;
        end
    end
end

endmodule