题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
reg [2:0] d1_reg;
reg [2:0] d2_reg;
reg [2:0] d3_reg;
wire [3:0] sum;

always @(posedge d1 or negedge rst)begin
	if(!rst)begin
		d1_reg <= 0;
	end
	else begin
		d1_reg <= d1_reg + 1;
	end
end

always @(posedge d2 or negedge rst)begin
	if(!rst)begin
		d2_reg <= 0;
	end
	else begin
		d2_reg <= d2_reg + 2;
	end
end

always @(posedge d3 or negedge rst)begin
	if(!rst)begin
		d3_reg <= 0;
	end
	else begin
		d3_reg <= d3_reg + 4;
	end
end

always @(posedge out1)begin
	d1_reg <= 0;
	d2_reg <= 0;
	d3_reg <= 0;
end


assign sum = d1_reg + d2_reg +d3_reg;


always @(posedge clk or negedge rst)begin
	if(!rst)begin
		out1 <= 1'b0;
		out2 <= 2'b00;
	end
	else begin
		if(sum >= 3)begin
			out1 <= 1'b1;
			out2 <= sum - 3;
		end
		else begin
			out1 <= 1'b0;
		    out2 <= 2'b00;
		end
	end
end

//*************code***********//
endmodule