题解 | #根据RTL图编写Verilog程序#
根据RTL图编写Verilog程序
https://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg q; wire q1; wire q2; always @(posedge clk or negedge rst_n)begin if(!rst_n)begin q <= 1'b0; end else begin q <= data_in; end end assign q1 = q; assign q2 = !q1 & data_in; always @(posedge clk or negedge rst_n)begin if(!rst_n)begin data_out <= 1'b0; end else begin data_out <= q2; end end endmodule
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