题解 | #串行进位加法器#

`timescale 1ns / 1ns

module add_4 (
    input [3:0] A,
    input [3:0] B,
    input       Ci,

    output wire [3:0] S,
    output wire       Co
);

    wire [4:1] C_reg;
    add_full add_full_inst1 (
        .A (A[0]),
        .B (B[0]),
        .Ci(Ci),

        .S (S[0]),
        .Co(C_reg[1])
    );

    generate
        genvar i;
        for (i = 1; i <= 3; i = i + 1) 
        begin : add_half_i
            add_full add_full_inst2 (
                .A (A[i]),
                .B (B[i]),
                .Ci(C_reg[i]),

                .S (S[i]),
                .Co(C_reg[i+1])
            );
        end

        assign Co = C_reg[4];

    endgenerate

endmodule

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire c_1;
wire c_2;
wire sum_1;

add_half add_half_1(
   .A   (A),
   .B   (B),
         
   .S   (sum_1),
   .C   (c_1)  
);
add_half add_half_2(
   .A   (sum_1),
   .B   (Ci),
         
   .S   (S),
   .C   (c_2)  
);

assign Co = c_1 | c_2;
endmodule